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<title>ARC (processor)</title>

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</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="Intel_Arc" title="Intel Arc">Intel Arc</a> or <a href="ARC_(specification)" title="ARC (specification)">ARC (specification)</a>.</div>

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</style><table class="infobox"><caption class="infobox-title">ARC</caption><tbody><tr><th scope="row" class="infobox-label">Designer</th><td class="infobox-data">ARC International PLC</td></tr><tr><th scope="row" class="infobox-label">Bits</th><td class="infobox-data"><a href="32-bit_computing" title="32-bit computing">32-bit</a>, <a href="64-bit_computing" title="64-bit computing">64-bit</a></td></tr><tr><th scope="row" class="infobox-label">Introduced</th><td class="infobox-data">1996<span style="display:none"> (<span class="bday dtstart published updated">1996</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Version</th><td class="infobox-data">ARCv3</td></tr><tr><th scope="row" class="infobox-label"><a href="Computer_architecture" title="Computer architecture">Design</a></th><td class="infobox-data"><a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></td></tr><tr><th scope="row" class="infobox-label">Type</th><td class="infobox-data"><a href="Load%E2%80%93store" class="mw-redirect" title="Load–store">Load–store</a></td></tr><tr><th scope="row" class="infobox-label"><a href="Instruction_set" class="mw-redirect" title="Instruction set">Encoding</a></th><td class="infobox-data">Variable (16- and 32-bit)</td></tr><tr><th scope="row" class="infobox-label"><a href="Branch_(computer_science)" title="Branch (computer science)">Branching</a></th><td class="infobox-data">Compare and branch</td></tr><tr><th scope="row" class="infobox-label"><a href="Endianness" title="Endianness">Endianness</a></th><td class="infobox-data">Bi</td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data">APEX user-defined instructions</td></tr><tr><th colspan="2" class="infobox-header"><a href="Processor_register" title="Processor register">Registers</a></th></tr><tr><td colspan="2" class="infobox-full-data">16 or 32 including SP user can increase to 60</td></tr></tbody></table>

<p><b>Argonaut RISC Core</b> (<b>ARC</b>) is a family of 32-bit and 64-bit <a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computer</a> (RISC) <a href="Central_processing_unit" title="Central processing unit">central processing units</a> (CPUs) originally designed by <a href="Synopsys#ARC_International" title="Synopsys">ARC International</a>.

</p><p>ARC processors are configurable and extensible for a wide range of uses in <a href="System_on_a_chip" title="System on a chip">system on a chip</a> (SoC) devices, including storage, digital home, mobile, automotive, and <a href="Internet_of_things" title="Internet of things">Internet of things</a> (IoT) applications. They have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year.<sup id="cite_ref-overcoming_1-0" class="reference"><a href="#cite_note-overcoming-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup>

</p><p>ARC processors employ the 16-/32-bit ARCompact <a href="Compressed_instruction_set" title="Compressed instruction set">compressed instruction set</a> <a href="Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA) that provides good performance and code density for embedded and host SoC applications.

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<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<p>The ARC concept was developed initially within <a href="Argonaut_Games" title="Argonaut Games">Argonaut Games</a> through a series of 3D pipeline development projects starting with the <a href="Super_FX" title="Super FX">Super FX</a> chip for the <a href="Super_Nintendo_Entertainment_System" title="Super Nintendo Entertainment System">Super Nintendo Entertainment System</a>.

</p><p>In 1995, Argonaut was split into Argonaut Technologies Limited (ATL), which had a variety of technology projects, and Argonaut Software Limited (ASL).

</p><p>At the start of 1996, the General Manager of Argonaut, John Edelson, started reducing ATL projects such as <a href="Argonaut_Games#BRender" title="Argonaut Games">BRender</a> and <a href="Motion_capture" title="Motion capture">motion capture</a> and investing in the development of the ARC concept. In September 1996 Rick Clucas decided that the value of the ARC processor was in other people using it rather than Argonaut doing projects using it and asked Bob Terwilliger to join as CEO; Rick Clucas then took on the role of CTO.

</p><p>In 1997, following investment by <a href="Apax_Partners" title="Apax Partners">Apax Partners</a>, ATL became ARC International and fully independent from Argonaut Games. Before their <a href="Initial_public_offering" title="Initial public offering">initial public offering</a> on the <a href="London_Stock_Exchange" title="London Stock Exchange">London Stock Exchange</a>, underwritten by <a href="Goldman_Sachs" title="Goldman Sachs">Goldman Sachs</a> and five other investment banks, three related technology companies were acquired: MetaWare in <a href="Santa_Cruz%2C_California" title="Santa Cruz, California">Santa Cruz, California</a> (development and modeling software),<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> VAutomation in <a href="Nashua%2C_New_Hampshire" title="Nashua, New Hampshire">Nashua, New Hampshire</a> (peripheral semiconductor IP), and Precise Software in <a href="Nepean%2C_Ontario" title="Nepean, Ontario">Nepean, Ontario</a> (RTOS).

</p><p>In 2009, ARC International was acquired by <a href="Virage_Logic" title="Virage Logic">Virage Logic</a>.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> In 2010, Virage was acquired by Synopsys, and ARC processors became part of the <a href="Synopsys" title="Synopsys">Synopsys</a> DesignWare series.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>

</p><p>In April 2020 Synopsys released the ARCv3 ISA with 64-bit support.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup>

</p><p>In November 2023, Synopsys released the <a href="RISC-V" title="RISC-V">RISC-V</a> compatible <i>ARC-V</i> processor IP as an extension of its ARC product line.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup>

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<div class="mw-heading mw-heading2"><h2 id="Design_configuration">Design configuration</h2></div>

<p>Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements.

</p><p>Configuration of the ARC processors occurs at design time, using the ARChitect processor configurator.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> The core was designed to be extensible, allowing designers to add their own custom instructions that can significantly increase performance or reduce power consumption.

</p><p>Unlike most <a href="Embedded_system" title="Embedded system">embedded</a> microprocessors, extra instructions, <a href="Hardware_register" title="Hardware register">registers</a>, and functions can be added in a modular fashion. Customers analyse the task, break down the operations, and then choose the appropriate extensions, or develop their own, to create their own custom microprocessor. They might optimise for speed, <a href="Energy_efficiency_(physics)" class="mw-redirect" title="Energy efficiency (physics)">energy efficiency</a>, or code density. Extensions can include, for example, a <a href="Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU), a fast <a href="Multiplier%E2%80%93accumulator" class="mw-redirect" title="Multiplier–accumulator">multiplier–accumulator</a>, a Universal Serial Bus (<a href="USB" title="USB">USB</a>) host, a <a href="Viterbi_algorithm" title="Viterbi algorithm">Viterbi path</a> decoder, or a user's proprietary RTL functions.

</p><p>The processors are <a href="FPGA" class="mw-redirect" title="FPGA">synthesizable</a> and can be implemented in any foundry or process, and are supported by a complete suite of development tools.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup>

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<ul><li><a href="List_of_common_microcontrollers" title="List of common microcontrollers">List of common microcontrollers</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison of instruction set architectures</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techdesignforums.com/practice/technique/power-performance-processor-ip/">"Overcoming the power/performance paradox in processor IP"</a>. <i>Tech Design Forums</i><span class="reference-accessdate">. Retrieved <span class="nowrap">13 August</span> 2014</span>.</cite></span>

</li>

<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite id="CITEREFAscierto1999" class="citation news cs1">Ascierto, Jerry (27 September 1999). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200721165255/https://www.edn.com/arc-acquires-metaware/">"ARC Acquires MetaWare"</a>. <i>EDN.com</i>. Archived from <a rel="nofollow" class="external text" href="https://www.edn.com/arc-acquires-metaware/">the original</a> on 21 July 2020.</cite></span>

</li>

<li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.eetimes.com/virage-logic-completes-acquisition-of-arc-international/">"Virage Logic completes acquisition of ARC International"</a>.</cite></span>

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<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://news.synopsys.com/home?item=123195">"Synopsys Completes Acquisition of Virage Logic Corporation"</a>. <i>news.synopsys.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">9 July</span> 2024</span>.</cite></span>

</li>

<li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://news.synopsys.com/2020-04-07-Synopsys-Introduces-New-64-bit-ARC-Processor-IP-Delivering-Up-to-3x-Performance-Increase-for-High-End-Embedded-Applications">"Synopsys Introduces New 64-bit ARC Processor IP"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220331110658/https://news.synopsys.com/2020-04-07-Synopsys-Introduces-New-64-bit-ARC-Processor-IP-Delivering-Up-to-3x-Performance-Increase-for-High-End-Embedded-Applications">Archived</a> from the original on 31 March 2022.</cite></span>

</li>

<li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><cite id="CITEREFWheeler2023" class="citation pressrelease cs1">Wheeler, Kelli (7 November 2023). <a rel="nofollow" class="external text" href="https://news.synopsys.com/2023-11-07-Synopsys-Expands-Its-ARC-Processor-IP-Portfolio-with-New-RISC-V-Family">"Synopsys Expands Its ARC Processor IP Portfolio with New RISC-V Family"</a> (Press release). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231107145315/https://news.synopsys.com/2023-11-07-Synopsys-Expands-Its-ARC-Processor-IP-Portfolio-with-New-RISC-V-Family">Archived</a> from the original on 7 November 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">7 November</span> 2023</span>.</cite></span>

</li>

<li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090422141606/http://www.arc.com/configurablecores/architect/">"ARChitect Processor Configurator"</a>. Arc.com. Archived from <a rel="nofollow" class="external text" href="http://www.arc.com/configurablecores/architect/">the original</a> on 22 April 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">2 March</span> 2014</span>.</cite></span>

</li>

<li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20161204101029/http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx">"Accelerating Development of Performance-Efficient SoCs"</a>. synopsys.com. Archived from <a rel="nofollow" class="external text" href="http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx">the original</a> on 4 December 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">13 August</span> 2014</span>.</cite></span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2></div>

<ul><li><a rel="nofollow" class="external text" href="https://www.eetimes.com/toshiba-arc-in-configurable-processor-collaboration/">Toshiba, ARC in configurable processor collaboration</a>, 15 May 2006</li>

<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070520164117/http://neasia.nikkeibp.com/neasia/004524">SPF: All About Power, Performance</a>, 30 June 2006</li>

<li><a rel="nofollow" class="external text" href="https://www.eetimes.com/architectures-programmable-arc-platform-targets-low-cost-multimedia/">Architectures: Programmable ARC platform targets low-cost multimedia</a>, 2 October 2006</li>

<li><a rel="nofollow" class="external text" href="https://www.eetimes.com/arc-adopts-clustered-parallelism-in-media-multiprocessing/">ARC adopts clustered parallelism in media multiprocessing</a>, 9 October 2006</li>

<li><a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1248611">ARC signs "landmark" licensing deal with Intel</a>, EE Times 9 November 2007</li></ul>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><span class="official-website"><span class="url"><a rel="nofollow" class="external text" href="http://www.synopsys.com/designware-ip/processor-solutions.html">Official website</a></span></span></li></ul>

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</style><div id="Programmable_logic116" style="font-size:114%;margin:0 4em"><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Logic_block" title="Logic block">Logic block</a></li></ul></li>

<li><a href="Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a>

<ul><li><a href="Xputer" title="Xputer">Xputer</a></li></ul></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li>

<li><a href="Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li>

<li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Verilog" title="Verilog">Verilog</a>

<li><a href="VHDL-VITAL" class="mw-redirect" title="VHDL-VITAL">VITAL</a></li></ul></li>

<li><a href="SystemVerilog" title="SystemVerilog">SystemVerilog</a>

<li><a href="SystemC" title="SystemC">SystemC</a></li>

<li><a href="Handel-C" title="Handel-C">Handel-C</a></li>

<li><a href="PALASM" title="PALASM">PALASM</a></li>

<li><a href="MyHDL" title="MyHDL">MyHDL</a></li>

<li><a href="Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Accellera" title="Accellera">Accellera</a></li>

<li><a href="Achronix" title="Achronix">Achronix</a></li>

<li><a href="Aldec" title="Aldec">Aldec</a></li>

<li><a href="Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li>

<li><a href="Infineon_Technologies" title="Infineon Technologies">Infineon</a></li>

<li><a href="Intel" title="Intel">Intel</a></li>

<li><a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li>

<li><a href="Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li>

<li><a href="Siemens" title="Siemens">Siemens</a></li>

<li><a href="Synopsys" title="Synopsys">Synopsys</a></li>

<li><a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Stratix" title="Stratix">Stratix</a></li>

<li><a href="Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Intel_Quartus_Prime" class="mw-redirect" title="Intel Quartus Prime">Intel Quartus Prime</a></li>

<li><a href="Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li>

<li><a href="Vivado" title="Vivado">Vivado</a></li>

<li><a href="ModelSim" title="ModelSim">ModelSim</a></li>

<li><a href="List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Intellectual_property" title="Intellectual property">Intellectual<br>property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul>

<li><a href="ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li>

<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li><a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>

<li><a href="OpenCores" title="OpenCores">OpenCores</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a>

<ul><li><a href="Libre-SOC" title="Libre-SOC">Libre-SOC</a></li>

<li><a href="OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li>

</div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Reduced_instruction_set_computer_(RISC)_architectures114" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Reduced_instruction_set_computer_(RISC)_architectures114" style="font-size:114%;margin:0 4em"><a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">Reduced instruction set computer</a> (RISC) architectures</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Origins</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Berkeley_RISC" title="Berkeley RISC">Berkeley RISC</a></li>

<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Development<br>active</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Blackfin" title="Blackfin">Analog Devices Blackfin</a></li>

<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a>, <a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a></li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li>

<li><a href="Renesas_Electronics" title="Renesas Electronics">Renesas</a> <a href="M32R" title="M32R">M32R</a>, <a href="SuperH" title="SuperH">SuperH</a>, <a href="V850" title="V850">V850</a></li>

<li><a href="SPARC" title="SPARC">SPARC</a></li>

<li><a href="Sunway_(processor)" title="Sunway (processor)">Sunway</a></li>

<li><a href="Unicore" title="Unicore">Unicore</a></li>

<li><a href="Xilinx" title="Xilinx">Xilinx</a> <a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a>, <a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Development<br>discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="DEC_Alpha" title="DEC Alpha">Alpha</a></li>

<li><a href="Apollo_PRISM" title="Apollo PRISM">Apollo PRISM</a></li>

<li><a href="Atmel" title="Atmel">Atmel</a> <a href="AVR32" title="AVR32">AVR32</a></li>

<li><a href="Clipper_architecture" title="Clipper architecture">Clipper</a></li>

<li><a href="AT%26T_Hobbit" title="AT&T Hobbit">CRISP</a></li>

<li><a href="DEC_PRISM" title="DEC PRISM">DEC PRISM</a></li>

<li><a href="Intel_i860" title="Intel i860">Intel i860</a>, <a href="Intel_i960" title="Intel i960">i960</a></li>

<li><a href="Motorola_88000" title="Motorola 88000">Motorola 88000</a>, <a href="M%C2%B7CORE" title="M·CORE">M·CORE</a></li>

<li><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a>, <a href="PowerPC" title="PowerPC">PowerPC</a> <i>(active use in space exploration as <a href="RAD750" title="RAD750">RAD750</a>)</i>, <a href="IBM_ROMP" title="IBM ROMP">ROMP</a></li></ul>

</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-07-07" href="https://en.wikipedia.org/wiki/?title=ARC_(processor)&oldid=1299300000">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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